Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * VIA VT8500 and WonderMedia WM8xxx UART Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - reg: base physical address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts: hardware interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clocks: shall be the input parent clock phandle for the clock. This should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	be the 24Mhz reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Aliases may be defined to ensure the correct ordering of the uarts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	aliases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		serial0 = &uart0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	uart0: serial@d8200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		compatible = "via,vt8500-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		reg = <0xd8200000 0x1040>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		interrupts = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		clocks = <&clkuart0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	};