Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible should contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   * "mediatek,mt2712-uart" for MT2712 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   * "mediatek,mt6755-uart" for MT6755 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   * "mediatek,mt6765-uart" for MT6765 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   * "mediatek,mt6779-uart" for MT6779 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   * "mediatek,mt6795-uart" for MT6795 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   * "mediatek,mt6797-uart" for MT6797 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   * "mediatek,mt7622-uart" for MT7622 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   * "mediatek,mt7623-uart" for MT7623 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   * "mediatek,mt7629-uart" for MT7629 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   * "mediatek,mt8127-uart" for MT8127 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   * "mediatek,mt8135-uart" for MT8135 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   * "mediatek,mt8173-uart" for MT8173 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   * "mediatek,mt8516-uart" for MT8516 compatible UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   * "mediatek,mt6577-uart" for MT6577 and all of the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - reg: The base address of the UART register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   index 0: an interrupt specifier for the UART controller itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)            support Rx in-band wake up. If one would like to use this feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)            one must create an addtional pinctrl to reconfigure Rx pin to normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)            GPIO before suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - clocks : Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   - "baud": The clock the baudrate is derived from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   - "bus": The bus clock for register accesses (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) For compatibility with older device trees an unnamed clock is used for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) baud clock if the baudclk does not exist. Do not use this for new designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	uart0: serial@11006000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		reg = <0x11006000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			     <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		clocks = <&uart_clk>, <&bus_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		clock-names = "baud", "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		pinctrl-names = "default", "sleep";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		pinctrl-0 = <&uart_pin>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		pinctrl-1 = <&uart_pin_sleep>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	};