^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : "snps,arc-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg : offset and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - interrupts : device interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - clock-frequency : the input clock frequency for the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - current-speed : baud rate for UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) arcuart0: serial@c0fc1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) compatible = "snps,arc-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) reg = <0xc0fc1000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) interrupts = <5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) clock-frequency = <80000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) current-speed = <115200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Note: Each port should have an alias correctly numbered in "aliases" node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) aliases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) serial0 = &arcuart0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };