^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/serial/8250.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: UART (Universal Asynchronous Receiver/Transmitter) bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - devicetree@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - $ref: /schemas/serial.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - aspeed,sirq-polarity-sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) const: aspeed,ast2500-vuart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const: mrvl,mmp-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) reg-shift:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - reg-shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) not:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - ns8250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - ns16450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - ns16550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - ns16550a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) anyOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - required: [ clock-frequency ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - required: [ clocks ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - const: ns8250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - const: ns16450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - const: ns16550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - const: ns16550a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - const: ns16850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - const: aspeed,ast2400-vuart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - const: aspeed,ast2500-vuart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - const: intel,xscale-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - const: mrvl,pxa-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - const: nuvoton,npcm750-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - const: nvidia,tegra20-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - const: nxp,lpc3220-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - altr,16550-FIFO32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - altr,16550-FIFO64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - altr,16550-FIFO128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - fsl,16550-FIFO64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - fsl,ns16550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) - andestech,uart16550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - nxp,lpc1850-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - opencores,uart16550-rtlsvn105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - ti,da830-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) - const: ns16550a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - ns16750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - cavium,octeon-3860-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) - xlnx,xps-uart16550-2.00.b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) - ralink,rt2880-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - ns16550 # Deprecated, unless the FIFO really is broken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - ns16550a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - ralink,mt7620a-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - ralink,rt3052-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - ralink,rt3883-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - const: ralink,rt2880-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) - ns16550 # Deprecated, unless the FIFO really is broken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) - ns16550a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) - mediatek,mt7622-btif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) - mediatek,mt7623-btif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - const: mediatek,mtk-btif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - const: mrvl,mmp-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - const: intel,xscale-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - nvidia,tegra30-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - nvidia,tegra114-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) - nvidia,tegra124-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - nvidia,tegra186-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) - nvidia,tegra194-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - nvidia,tegra210-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - const: nvidia,tegra20-uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clock-frequency: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) resets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) current-speed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) $ref: /schemas/types.yaml#definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) description: The current active speed of the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg-offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) Offset to apply to the mapbase from the start of the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg-shift:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) description: Quantity to shift the register offsets by.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg-io-width:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) The size (in bytes) of the IO accesses that should be performed on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) device. There are some systems that require 32-bit accesses to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) UART (e.g. TI davinci).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) used-by-rtas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) Set to indicate that the port is in use by the OpenFirmware RTAS and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) should not be registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) no-loopback-test:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) Set to indicate that the port does not implement loopback test mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) fifo-size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) $ref: /schemas/types.yaml#definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) description: The fifo size of the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) auto-flow-control:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) One way to enable automatic flow control support. The driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) allowed to detect support for the capability even without this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tx-threshold:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) $ref: /schemas/types.yaml#definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) Specify the TX FIFO low water indication for parts with programmable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) TX FIFO thresholds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) overrun-throttle-ms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) How long to pause uart rx when input overrun is encountered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rts-gpios: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cts-gpios: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dtr-gpios: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dsr-gpios: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rng-gpios: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dcd-gpios: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) aspeed,sirq-polarity-sense:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) $ref: /schemas/types.yaml#/definitions/phandle-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) Phandle to aspeed,ast2500-scu compatible syscon alongside register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) offset and bit number to identify how the SIRQ polarity should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) configured. One possible data source is the LPC/eSPI mode bit. Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) applicable to aspeed,ast2500-vuart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) serial@80230000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) compatible = "ns8250";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) reg = <0x80230000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) interrupts = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clock-frequency = <48000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #include <dt-bindings/gpio/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) serial@49042000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) compatible = "andestech,uart16550", "ns16550a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) reg = <0x49042000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) interrupts = <80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clock-frequency = <48000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #include <dt-bindings/clock/aspeed-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) serial@1e787000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) compatible = "aspeed,ast2500-vuart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg = <0x1e787000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) interrupts = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clocks = <&syscon ASPEED_CLK_APB>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) no-loopback-test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ...
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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