^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * HiSilicon SAS controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The HiSilicon SAS controller supports SAS/SATA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Main node required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible : value should be as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - sas-addr : array of 8 bytes for host SAS address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg : Contains two regions. The first is the address and length of the SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) register. The second is the address and length of CPLD register for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) SGPIO control. The second is optional, and should be set only when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) we use a CPLD for directly attached disk LED control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - hisilicon,sas-syscon: phandle of syscon used for sas control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - ctrl-reset-reg : offset to controller reset register in ctrl reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - queue-count : number of delivery and completion queues in the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - phy-count : number of phys accessible by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) sources; the interrupts are ordered in 3 groups, as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - Phy interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - Completion queue interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - Fatal interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Phy interrupts : Each phy has 3 interrupt sources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - broadcast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - phyup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - abnormal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) The phy interrupts are ordered into groups of 3 per phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (broadcast, phyup, and abnormal) in increasing order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Completion queue interrupts : each completion queue has 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) interrupt source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) The interrupts are ordered in increasing order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Fatal interrupts : the fatal interrupts are ordered as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - AXI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) For v2 hw: Interrupts for phys, Sata, and completion queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) the interrupts are ordered in 3 groups, as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - Phy interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - Sata interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - Completion queue interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Phy interrupts : Each controller has 2 phy interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - phy up/down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - channel interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Sata interrupts : Each phy on the controller has 1 Sata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) interrupt. The interrupts are ordered in increasing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Completion queue interrupts : each completion queue has 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) interrupt source. The interrupts are ordered in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) increasing order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Optional main node properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "am-max-transmissions" limitation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - hisilicon,signal-attenuation : array of 3 32-bit values, containing de-emphasis,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) preshoot, and boost attenuation readings for the board. They
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) are used to describe the signal attenuation of the board. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) values' range is 7600 to 12400, and used to represent -24dB to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 24dB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) The formula is "y = (x-10000)/10000". For example, 10478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) means 4.78dB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) sas0: sas@c1000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) compatible = "hisilicon,hip05-sas-v1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) sas-addr = [50 01 88 20 16 00 00 0a];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg = <0x0 0xc1000000 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) hisilicon,sas-syscon = <&pcie_sas>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ctrl-reset-reg = <0xa60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ctrl-reset-sts-reg = <0x5a30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ctrl-clock-ena-reg = <0x338>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) queue-count = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) phy-count = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) interrupt-parent = <&mbigen_dsa>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) <269 4>,<273 4>,<274 4>,/* phy1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) <279 4>,<283 4>,<284 4>,/* phy2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) <289 4>,<293 4>,<294 4>,/* phy3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) <299 4>,<303 4>,<304 4>,/* phy4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) <309 4>,<313 4>,<314 4>,/* phy5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) <319 4>,<323 4>,<324 4>,/* phy6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) <329 4>,<333 4>,<334 4>,/* phy7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) <336 1>,<337 1>,<338 1>,/* cq0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) <339 1>,<340 1>,<341 1>,/* cq3-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) <342 1>,<343 1>,<344 1>,/* cq6-8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) <345 1>,<346 1>,<347 1>,/* cq9-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) <348 1>,<349 1>,<350 1>,/* cq12-14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) <351 1>,<352 1>,<353 1>,/* cq15-17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) <354 1>,<355 1>,<356 1>,/* cq18-20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) <357 1>,<358 1>,<359 1>,/* cq21-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) <360 1>,<361 1>,<362 1>,/* cq24-26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) <363 1>,<364 1>,<365 1>,/* cq27-29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <366 1>,<367 1>/* cq30-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) <376 4>,/* fatal ecc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <381 4>;/* fatal axi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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