Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) RTC controller for the Xilinx Zynq MPSoC Real Time Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Separate IRQ lines for seconds and alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible: Should be "xlnx,zynqmp-rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: Physical base address of the controller and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)        of memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts: IRQ lines for the RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupt-names: interrupt line names eg. "sec" "alarm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Optional:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - calibration: calibration value for 1 sec period which will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		be programmed directly to calibration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) rtc: rtc@ffa60000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	compatible = "xlnx,zynqmp-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	reg = <0x0 0xffa60000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	interrupts = <0 26 4>, <0 27 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	interrupt-names = "alarm", "sec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	calibration = <0x198233>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };