^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * APM X-Gene Real Time Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) RTC controller for the APM X-Gene Real Time Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible : Should be "apm,xgene-rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - interrupts: IRQ line for the RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #clock-cells: Should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks: Reference to the clock entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) rtcclk: rtcclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) clock-frequency = <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) clock-output-names = "rtcclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) rtc: rtc@10510000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) compatible = "apm,xgene-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) reg = <0x0 0x10510000 0x0 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) interrupts = <0x0 0x46 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) clocks = <&rtcclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };