^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * STMP3xxx/i.MX28 Time Clock controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * "fsl,stmp3xxx-rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - interrupts: rtc alarm interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - stmp,crystal-freq: override crystal frequency as determined from fuse bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Only <32000> and <32768> are possible for the hardware. Use <0> for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "no crystal".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) rtc@80056000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0x80056000 2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) interrupts = <29>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };