Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Rockchip rk timer RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   "rockchip,rk3308-timer-rtc": for Rockchip RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg: base address of the timer register and length of memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - interrupts: should contain the interrupts for the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clocks : must contain an entry for each entry in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names : must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   "timer", "pclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	rk_timer_rtc: rk-timer-rtc@ff1a0020 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		compatible = "rockchip,rk3308-timer-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		reg = <0x0 0xff1a0020 0x0 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		clock-names = "pclk", "timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	};