^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Device-Tree bindings for MediaTek SoC based RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : Should be "mediatek,mt2712-rtc" : for MT2712 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg : Specifies base physical address and size of the registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - interrupts : Should contain the interrupt for RTC alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) rtc: rtc@10011000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) compatible = "mediatek,mt2712-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) reg = <0 0x10011000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) };