^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * NXP LPC32xx SoC Real Time Clock controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: must be "nxp,lpc3220-rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts: The RTC interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) rtc@40024000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) compatible = "nxp,lpc3220-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) reg = <0x40024000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) interrupts = <52 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };