^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Real Time Clock of the Armada 38x/7K/8K SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) RTC controller for the Armada 38x, 7K and 8K SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible : Should be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "marvell,armada-380-rtc" for Armada 38x SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg: a list of base address and size pairs, one for each entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) reg-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg names: should contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * "rtc" for the RTC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * "rtc-soc" for the SoC related registers and among them the one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) related to the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - interrupts: IRQ line for the RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) rtc@a3800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) compatible = "marvell,armada-380-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) reg = <0xa3800 0x20>, <0x184a0 0x0c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) reg-names = "rtc", "rtc-soc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };