^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Device-Tree bindings for Mediatek random number generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) found in MediaTek SoC family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible : Should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "mediatek,mt7622-rng", "mediatek,mt7623-rng" : for MT7622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "mediatek,mt7629-rng", "mediatek,mt7623-rng" : for MT7629
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "mediatek,mt7623-rng" : for MT7623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "mediatek,mt8516-rng", "mediatek,mt7623-rng" : for MT8516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks : list of clock specifiers, corresponding to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) entries in clock-names property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clock-names : Should contain "rng" entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg : Specifies base physical address and size of the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) rng: rng@1020f000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "mediatek,mt7623-rng";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0 0x1020f000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) clocks = <&infracfg CLK_INFRA_TRNG>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) clock-names = "rng";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };