Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Rockchip SFC Controller for SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : "rockchip,sfc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg : shall contain registers location and length for data and reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts : shall define the nand controller interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - clocks : shall reference sfc controller clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clock-names : sfc controller internal clock names. Shall contain :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)     * "clk_sfc" : sfc controller clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)     * "hclk_sfc" : sfc ahb clock gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - assigned-clocks : sclk preset by dts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - assigned-clock-frequency : sclk frequency, io clk = sclk/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) sfc: sfc@301c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	compatible = "rockchip,sfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	reg = <0x301c0000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	clocks = <&clk_sfc>, <&clk_gates15 10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	clock-names = "clk_sfc", "hclk_sfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	assigned-clocks = <&cru SCLK_SFC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	assigned-clock-frequency = <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };