Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Rockchip NANDC Controller for SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : "rockchip,rk-nandc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg : shall contain registers location and length for data and reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts : shall define the nandc controller interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - nandc_id : shall reference the number of nandc controllers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clocks : shall reference nandc controller clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names : nandc controller internal clock names. Shall contain :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)     * "clk_nandc" : nand controller clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)     * "hclk_nandc" : nandc ahb clock gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)     * "g_clk_nandc" : nandc enable clock gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) nandc: nandc@30100000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	compatible = "rockchip,rk-nandc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	reg = <0x0 0xff4b0000 0x0 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	nandc_id = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	clocks = <&clk_nandc>, <&clk_gates15 3>, <&clk_gates5 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	clock-names = "clk_nandc", "hclk_nandc", "g_clk_nandc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };