^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/riscv/cpus.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: RISC-V bindings for 'cpus' DT nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Paul Walmsley <paul.walmsley@sifive.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Palmer Dabbelt <palmer@sifive.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This document uses some terminology common to the RISC-V community
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) that is not widely used, the definitions of which are listed here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) hart: A hardware execution context, which contains all the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) mandated by the RISC-V ISA: a PC and some registers. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) terminology is designed to disambiguate software's view of execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) contexts from any particular microarchitectural implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) strategy. For example, an Intel laptop containing one socket with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) two cores, each of which has two hyperthreads, could be described as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) having four harts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - sifive,rocket0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - sifive,e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - sifive,e51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - sifive,u54-mc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - sifive,u54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - sifive,u5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - const: riscv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - const: riscv # Simulator only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Identifies that the hart uses the RISC-V instruction set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) and identifies the type of the hart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mmu-type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Identifies the MMU address translation mode used on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) hart. These values originate from the RISC-V Privileged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Specification document, available from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) https://riscv.org/specifications/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) $ref: "/schemas/types.yaml#/definitions/string"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - riscv,sv32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - riscv,sv39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - riscv,sv48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) riscv,isa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Identifies the specific RISC-V instruction set architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) supported by the hart. These are documented in the RISC-V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) User-Level ISA document, available from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) https://riscv.org/specifications/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) While the isa strings in ISA specification are case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) insensitive, letters in the riscv,isa string must be all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) lowercase to simplify parsing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) $ref: "/schemas/types.yaml#/definitions/string"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - rv64imac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - rv64imafdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) timebase-frequency: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) interrupt-controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) type: object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) description: Describes the CPU's local interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) '#interrupt-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const: riscv,cpu-intc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) interrupt-controller: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - '#interrupt-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - interrupt-controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) - riscv,isa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - interrupt-controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) additionalProperties: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) // Example 1: SiFive Freedom U540G Development Kit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) timebase-frequency = <1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clock-frequency = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) compatible = "sifive,rocket0", "riscv";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) i-cache-block-size = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) i-cache-sets = <128>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) i-cache-size = <16384>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) riscv,isa = "rv64imac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cpu_intc0: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) compatible = "riscv,cpu-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clock-frequency = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) compatible = "sifive,rocket0", "riscv";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) d-cache-block-size = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) d-cache-sets = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) d-cache-size = <32768>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) d-tlb-sets = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) d-tlb-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) i-cache-block-size = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) i-cache-sets = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) i-cache-size = <32768>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) i-tlb-sets = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) i-tlb-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mmu-type = "riscv,sv39";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) riscv,isa = "rv64imafdc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tlb-split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cpu_intc1: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) compatible = "riscv,cpu-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) // Example 2: Spike ISA Simulator with 1 Hart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) compatible = "riscv";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) riscv,isa = "rv64imafdc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mmu-type = "riscv,sv48";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) compatible = "riscv,cpu-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ...
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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