Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Xilinx Zynq Reset Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Zynq AP-SoC has several different resets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: "xlnx,zynq-reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: SLCR offset and size taken via syscon <0x200 0x48>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - syscon: <&slcr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   This should be a phandle to the Zynq's SLCR registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #reset-cells: Must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) The Zynq Reset Manager needs to be a childnode of the SLCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	rstc: rstc@200 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		compatible = "xlnx,zynq-reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		reg = <0x200 0x48>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		#reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		syscon = <&slcr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Reset outputs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  0  : soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  32 : ddr reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  64 : topsw reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  96 : dmac reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  128: usb0 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  129: usb1 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  160: gem0 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  161: gem1 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  164: gem0 rx reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  165: gem1 rx reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  166: gem0 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  167: gem1 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  192: sdio0 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  193: sdio1 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  196: sdio0 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  197: sdio1 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  224: spi0 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  225: spi1 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  226: spi0 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  227: spi1 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  256: can0 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  257: can1 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  258: can0 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  259: can1 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  288: i2c0 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  289: i2c1 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  320: uart0 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  321: uart1 reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  322: uart0 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  323: uart1 ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  352: gpio reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  384: lqspi reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  385: qspi ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  416: smc reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  417: smc ref reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  448: ocm reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  512: fpga0 out reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  513: fpga1 out reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  514: fpga2 out reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)  515: fpga3 out reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)  544: a9 reset 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)  545: a9 reset 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)  552: peri reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)