Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) UniPhier glue reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Peripheral core reset in glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) -----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Some peripheral core reset belongs to its own glue layer. Before using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) this core reset, it is necessary to control the clocks and resets to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) this layer. These clocks and resets should be described in each property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible: Should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)     "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)     "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)     "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)     "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)     "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - #reset-cells: Should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - reg: Specifies offset and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - clocks: A list of phandles to the clock gate for the glue layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	According to the clock-names, appropriate clocks are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clock-names: Should contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)     "gio", "link" - for Pro4 and Pro5 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     "link"        - for others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - resets: A list of phandles to the reset control for the glue layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	According to the reset-names, appropriate resets are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - reset-names: Should contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     "gio", "link" - for Pro4 and Pro5 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)     "link"        - for others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	usb-glue@65b00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "socionext,uniphier-ld20-dwc3-glue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			     "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		ranges = <0 0x65b00000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		usb_rst: reset@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			compatible = "socionext,uniphier-ld20-usb3-reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			reg = <0x0 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			#reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			clock-names = "link";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			clocks = <&sys_clk 14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			reset-names = "link";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			resets = <&sys_rst 14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	};