^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) TI SysCon Reset Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Almost all SoCs have hardware modules that require reset control in addition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) to clock and power control for their functionality. The reset control is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) typically provided by means of memory-mapped I/O registers. These registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) sometimes a part of a larger register space region implementing various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) functionalities. This register range is best represented as a syscon node to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) allow multiple entities to access their relevant registers in the common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) A SysCon Reset Controller node defines a device that uses a syscon node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) and provides reset management functionality for various hardware modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) present on the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) SysCon Reset Controller Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Each of the reset provider/controller nodes should be a child of a syscon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) node and have the following properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - compatible : Should be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "ti,k2e-pscrst"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "ti,k2l-pscrst"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "ti,k2hk-pscrst"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "ti,syscon-reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - #reset-cells : Should be 1. Please see the reset consumer node below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) for usage details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - ti,reset-bits : Contains the reset control register information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Should contain 7 cells for each reset exposed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) consumers, defined as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Cell #1 : offset of the reset assert control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) register from the syscon register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Cell #2 : bit position of the reset in the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) assert control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Cell #3 : offset of the reset deassert control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) register from the syscon register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Cell #4 : bit position of the reset in the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) deassert control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Cell #5 : offset of the reset status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) from the syscon register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Cell #6 : bit position of the reset in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) reset status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Cell #7 : Flags used to control reset behavior,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) availible flags defined in the DT include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) file <dt-bindings/reset/ti-syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SysCon Reset Consumer Nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ===========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Each of the reset consumer nodes should have the following properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) in addition to their own properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - resets : A phandle to the reset controller node and an index number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) to a reset specifier as defined above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) common reset controller usage by consumers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) The following example demonstrates a syscon node, the reset controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 66AK2E SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) psc: power-sleep-controller@2350000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) compatible = "syscon", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = <0x02350000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pscrst: reset-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) compatible = "ti,k2e-pscrst", "ti,syscon-reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ti,reset-bits = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0xa40 5 0xa44 3 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) /* 1: example */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dsp0: dsp0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) resets = <&pscrst 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
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