^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Altera SOCFPGA Reset Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg : Should contain 1 register ranges(address and length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - altr,modrst-offset : Should contain the offset of the first modrst register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - #reset-cells: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) rstmgr@ffd05000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) compatible = "altr,rst-mgr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) reg = <0xffd05000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) altr,modrst-offset = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };