Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) STMicroelectronics Co-Processor Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ----------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) This binding provides support for adjunct processors found on ST SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Co-processors can be controlled from the bootloader or the primary OS. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) the bootloader starts a co-processor, the primary OS must detect its state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) and act accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible		Should be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 				"st,st231-rproc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 				"st,st40-rproc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - memory-region		Reserved memory (See: ../reserved-memory/reserved-memory.txt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - resets		Reset lines (See: ../reset/reset.txt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reset-names		Must be "sw_reset" and "pwr_reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks		Clock for co-processor (See: ../clock/clock-bindings.txt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clock-frequency	Clock frequency to set co-processor at if the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			hasn't already done so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - st,syscfg		System configuration register which holds the boot vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			for the co-processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 				1st cell: Phandle to syscon block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 				2nd cell: Boot vector register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	audio_reserved: rproc@42000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		compatible = "shared-dma-pool";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		reg = <0x42000000 0x01000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		no-map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	st231-audio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		compatible	= "st,st231-rproc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		memory-region	= <&audio_reserved>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		resets		= <&softreset STIH407_ST231_AUD_SOFTRESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		reset-names	= "sw_reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		clocks		= <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		clock-frequency	= <600000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		st,syscfg	= <&syscfg_core 0x228>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	};