Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should be "via,vt8500-pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: physical base address and length of the controller's registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   the cells format. The only third cell flag supported by this binding is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   PWM_POLARITY_INVERTED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clocks: phandle to the PWM source clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) pwm1: pwm@d8220000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	compatible = "via,vt8500-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	reg = <0xd8220000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	clocks = <&clkpwm>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };