Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ZTE ZX PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible: Should be "zte,zx296718-pwm".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  - reg: Physical base address and length of the controller's registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  - clocks : The phandle and specifier referencing the controller's clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)    PCLK is for register access, while WCLK is the reference clock for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)    calculating period and duty cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)    the cells format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	pwm: pwm@1439000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		compatible = "zte,zx296718-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		reg = <0x1439000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		clocks = <&lsp1crm LSP1_PWM_PCLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			 <&lsp1crm LSP1_PWM_WCLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		clock-names = "pclk", "wclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	};