Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) TI SOC EHRPWM based PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Must be "ti,<soc>-ehrpwm".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   for am33xx  - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   for am4372  - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   for am654   - compatible = "ti,am654-ehrpwm", "ti-am3352-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   for da850   - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   the cells format. The only third cell flag supported by this binding is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   PWM_POLARITY_INVERTED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: physical base address and size of the registers map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clocks: Handle to the PWM's time-base and functional clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clock-names: Must be set to "tbclk" and "fck".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	reg = <0x48300200 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	clock-names = "tbclk", "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	reg = <0x48300200 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	clock-names = "tbclk", "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	ti,hwmods = "ehrpwm0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	reg = <0x1f00000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	reg = <0x4843e200 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	clock-names = "tbclk", "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };