Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Spreadtrum PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Spreadtrum SoCs PWM controller provides 4 PWM channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible : Should be "sprd,ums512-pwm".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - reg: Physical base address and length of the controller's registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clocks: The phandle and specifier referencing the controller's clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names: Should contain following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   the cells format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - assigned-clocks: Reference to the PWM clock entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - assigned-clock-parents: The phandle of the parent clock of PWM clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	pwms: pwm@32260000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		compatible = "sprd,ums512-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		reg = <0 0x32260000 0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		clock-names = "pwm0", "enable0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			"pwm1", "enable1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			"pwm2", "enable2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			"pwm3", "enable3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		       <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		       <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		       <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		assigned-clocks = <&aon_clk CLK_PWM0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			<&aon_clk CLK_PWM1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			<&aon_clk CLK_PWM2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			<&aon_clk CLK_PWM3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		assigned-clock-parents = <&ext_26m>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			<&ext_26m>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			<&ext_26m>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			<&ext_26m>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		#pwm-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	};