Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Rockchip PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible: should be "rockchip,<name>-pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)    "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)    "rockchip,rk3288-pwm": found on RK3288 SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)    "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)    "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - reg: physical base address and length of the controller's registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - clocks: See ../clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)    - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)      - There is one clock that's used both to derive the functional clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)        for the device and as the bus clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)    - For newer hardware (rk3328 and future socs): specified by name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)      - "pwm": This is used to derive the functional clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)      - "pclk": This is the APB bus clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.yaml in this directory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)    for a description of the cell format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	pwm0: pwm@20030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		compatible = "rockchip,rk2928-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		reg = <0x20030000 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		clocks = <&cru PCLK_PWM01>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		#pwm-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	};