Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) MediaTek display PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible: should be "mediatek,<name>-disp-pwm":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)    - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)    - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)    - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - reg: physical base address and length of the controller's registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)    the cell format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - clocks: phandle and clock specifier of the PWM reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - clock-names: must contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)    - "main": clock used to generate PWM signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)    - "mm": sync signals from the modules of mmsys.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - pinctrl-names: Must contain a "default" entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - pinctrl-0: One property must exist for each entry in pinctrl-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)    See pinctrl/pinctrl-bindings.txt for details of the property values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	pwm0: pwm@1401e000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		compatible = "mediatek,mt8173-disp-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			     "mediatek,mt6595-disp-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		reg = <0 0x1401e000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		#pwm-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		clocks = <&mmsys CLK_MM_DISP_PWM026M>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			 <&mmsys CLK_MM_DISP_PWM0MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clock-names = "main", "mm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		pinctrl-0 = <&disp_pwm0_pins>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	backlight_lcd: backlight_lcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		compatible = "pwm-backlight";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		pwms = <&pwm0 0 1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		brightness-levels = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			  0  16  32  48  64  80  96 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			128 144 160 176 192 208 224 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		default-brightness-level = <9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		power-supply = <&mt6397_vio18_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	};