Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Amlogic Meson PWM Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible: Shall contain "amlogic,meson8b-pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)                          or "amlogic,meson-gxbb-pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)                          or "amlogic,meson-gxbb-ao-pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)                          or "amlogic,meson-axg-ee-pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)                          or "amlogic,meson-axg-ao-pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)                          or "amlogic,meson-g12a-ee-pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)                          or "amlogic,meson-g12a-ao-pwm-ab"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                          or "amlogic,meson-g12a-ao-pwm-cd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   the cells format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks: Could contain one or two parents clocks phandle for each of the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   PWM channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clock-names: Could contain at least the "clkin0" and/or "clkin1" names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	pwm_ab: pwm@8550 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		compatible = "amlogic,meson-gxbb-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		reg = <0x0 0x08550 0x0 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clocks = <&xtal>, <&xtal>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		clock-names = "clkin0", "clkin1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	}