Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) MediaTek PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible: should be "mediatek,<name>-pwm":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)    - "mediatek,mt2712-pwm": found on mt2712 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)    - "mediatek,mt7622-pwm": found on mt7622 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)    - "mediatek,mt7623-pwm": found on mt7623 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)    - "mediatek,mt7628-pwm": found on mt7628 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)    - "mediatek,mt7629-pwm": found on mt7629 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)    - "mediatek,mt8516-pwm": found on mt8516 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - reg: physical base address and length of the controller's registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)    the cell format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - clocks: phandle and clock specifier of the PWM reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - clock-names: must contain the following, except for MT7628 which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)                 has no clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)    - "top": the top clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)    - "main": clock used by the PWM core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)    - "pwm1-8": the eight per PWM clocks for mt2712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    - "pwm1-6": the six per PWM clocks for mt7622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)    - "pwm1-5": the five per PWM clocks for mt7623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)    - "pwm1"  : the PWM1 clock for mt7629
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  - pinctrl-names: Must contain a "default" entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  - pinctrl-0: One property must exist for each entry in pinctrl-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)    See pinctrl/pinctrl-bindings.txt for details of the property values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - assigned-clocks: Reference to the PWM clock entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - assigned-clock-parents: The phandle of the parent clock of PWM clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	pwm0: pwm@11006000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		compatible = "mediatek,mt7623-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		reg = <0 0x11006000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		#pwm-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		clocks = <&topckgen CLK_TOP_PWM_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			 <&pericfg CLK_PERI_PWM>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			 <&pericfg CLK_PERI_PWM1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			 <&pericfg CLK_PERI_PWM2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			 <&pericfg CLK_PERI_PWM3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			 <&pericfg CLK_PERI_PWM4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			 <&pericfg CLK_PERI_PWM5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		clock-names = "top", "main", "pwm1", "pwm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			      "pwm3", "pwm4", "pwm5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		pinctrl-0 = <&pwm0_pins>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	};