Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Freescale FlexTimer Module (FTM) PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The same FTM PWM device can have a different endianness on different SoCs. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) device tree provides a property to describing this so that an operating system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) device driver can handle all variants of the device. Refer to the table below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) for the endianness of the FTM PWM block as integrated into the existing SoCs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	SoC     | FTM-PWM endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	--------+-------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	Vybrid  | LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	LS1     | BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	LS2     | LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Please see ../regmap/regmap.txt for more detail about how to specify endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) modes in device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    compatible strings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - reg: Physical base address and length of the controller's registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   the cells format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - clock-names: Should include the following module clock source entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     "ftm_sys" (module clock, also can be used as counter clock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     "ftm_ext" (external counter clock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)     "ftm_fix" (fixed counter clock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)     "ftm_cnt_clk_en" (external and fixed counter clock enable/disable).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - clocks: Must contain a phandle and clock specifier for each entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   clock-names, please see clock/clock-bindings.txt for details of the property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - pinctrl-names: Must contain a "default" entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - pinctrl-NNN: One property must exist for each entry in pinctrl-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   See pinctrl/pinctrl-bindings.txt for details of the property values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - big-endian: Boolean property, required if the FTM PWM registers use a big-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   endian rather than little-endian layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pwm0: pwm@40038000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		compatible = "fsl,vf610-ftm-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		reg = <0x40038000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		clock-names = "ftm_sys", "ftm_ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 				"ftm_fix", "ftm_cnt_clk_en";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		clocks = <&clks VF610_CLK_FTM0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			<&clks VF610_CLK_FTM0_EXT_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			<&clks VF610_CLK_FTM0_FIX_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		pinctrl-0 = <&pinctrl_pwm0_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		big-endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };