Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Freescale i.MX TPM PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Anson Huang <anson.huang@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   The TPM counter and period counter are shared between multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   channels, so all channels should use same period setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   "#pwm-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     const: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)     enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       - fsl,imx7ulp-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   assigned-clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   assigned-clock-parents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)   - "#pwm-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)     #include <dt-bindings/clock/imx7ulp-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)     pwm@40250000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)         compatible = "fsl,imx7ulp-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)         reg = <0x40250000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)         assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)         assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)         clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)         #pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)     };