Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Freescale i.MX PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Philipp Zabel <p.zabel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   "#pwm-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)     description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)       Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)       in this directory for a description of the cells format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)     enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)       - 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)       - 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)       - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)           - fsl,imx1-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)           - fsl,imx27-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)       - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)           - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)               - fsl,imx25-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)               - fsl,imx31-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)               - fsl,imx50-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)               - fsl,imx51-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)               - fsl,imx53-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)               - fsl,imx6q-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)               - fsl,imx6sl-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)               - fsl,imx6sll-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)               - fsl,imx6sx-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)               - fsl,imx6ul-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)               - fsl,imx7d-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)               - fsl,imx8mm-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)               - fsl,imx8mn-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)               - fsl,imx8mp-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)               - fsl,imx8mq-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)           - const: fsl,imx27-pwm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)       - description: SoC PWM ipg clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)       - description: SoC PWM per clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)       - const: ipg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)       - const: per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)   - "#pwm-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)     #include <dt-bindings/clock/imx5-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)     pwm@53fb4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)         #pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)         compatible = "fsl,imx27-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)         reg = <0x53fb4000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)         clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)                  <&clks IMX5_CLK_PWM1_HF_GATE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)         clock-names = "ipg", "per";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)         interrupts = <61>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)     };