^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) # (C) COPYRIGHT 2017, 2019-2021 ARM Limited. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) # This program is free software and is provided to you under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) # GNU General Public License version 2 as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) # Foundation, and any use by you of this program is subject to the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) # of such GNU license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) # This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) # but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) # GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) # You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) # along with this program; if not, you can access it online at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) # http://www.gnu.org/licenses/gpl-2.0.html.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ARM Mali Midgard OPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * OPP Table Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) This describes the OPPs belonging to a device. This node can have following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - compatible: Allow OPPs to express their compatibility. It should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "operating-points-v2", "operating-points-v2-mali".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - OPP nodes: One or more OPP nodes describing voltage-current-frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) combinations. Their name isn't significant but their phandle can be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) reference an OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * OPP Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) This defines voltage-current-frequency combinations along with other related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - opp-hz: Nominal frequency in Hz, expressed as a 64-bit big-endian integer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) This should be treated as a relative performance measurement, taking both GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) frequency and core mask into account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - opp-hz-real: List of one or two real frequencies in Hz, expressed as 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) big-endian integers. They shall correspond to the clocks declared under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) the Mali device node, and follow the same order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - opp-core-mask: Shader core mask. If neither this or opp-core-count are present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) then all shader cores will be used for this OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - opp-core-count: Number of cores to use for this OPP. If this is present then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) the driver will build a core mask using the available core mask provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) the GPU hardware. An opp-core-count value of 0 is not permitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) If neither this nor opp-core-mask are present then all shader cores will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) used for this OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) If both this and opp-core-mask are present then opp-core-mask is ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - opp-microvolt: List of one or two voltages in micro Volts. They shall correspond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) to the regulators declared under the Mali device node, and follow the order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "logic", "memory".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) A single regulator's voltage is specified with an array of size one or three.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Single entry is for target voltage and three entries are for <target min max>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) voltages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Entries for multiple regulators must be present in the same order as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) regulators are specified in device's DT node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - opp-microvolt-<name>: Named opp-microvolt property. This is exactly similar to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) the above opp-microvolt property, but allows multiple voltage ranges to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) provided for the same OPP. At runtime, the platform can pick a <name> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) matching opp-microvolt-<name> property will be enabled for all OPPs. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) platform doesn't pick a specific <name> or the <name> doesn't match with any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) opp-microvolt-<name> properties, then opp-microvolt property shall be used, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - opp-microamp: The maximum current drawn by the device in microamperes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) considering system specific parameters (such as transients, process, aging,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) maximum operating temperature range etc.) as necessary. This may be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) set the most efficient regulator operating mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Should only be set if opp-microvolt is set for the OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) Entries for multiple regulators must be present in the same order as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regulators are specified in device's DT node. If this property isn't required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) for few regulators, then this should be marked as zero for them. If it isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) required for any regulator, then this property need not be present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - opp-microamp-<name>: Named opp-microamp property. Similar to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) opp-microvolt-<name> property, but for microamp instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - clock-latency-ns: Specifies the maximum possible transition latency (in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) nanoseconds) for switching to this OPP from any other OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) available on some platforms, where the device can run over its operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) frequency for a short duration of time limited by the device's power, current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) and thermal limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - opp-suspend: Marks the OPP to be used during device suspend. Only one OPP in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) the table should have this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) - opp-mali-errata-1485982: Marks the OPP to be selected for suspend clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) This will be effective only if MALI_HW_ERRATA_1485982_USE_CLOCK_ALTERNATIVE is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enabled. It needs to be placed in any OPP that has proper suspend clock for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) the HW workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) - opp-supported-hw: This enables us to select only a subset of OPPs from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) larger OPP table, based on what version of the hardware we are running on. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) still can't have multiple nodes with the same opp-hz value in OPP table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) It's an user defined array containing a hierarchy of hardware version numbers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) supported by the OPP. For example: a platform with hierarchy of three levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) of versions (A, B and C), this field should be like <X Y Z>, where X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) corresponds to Version hierarchy A, Y corresponds to version hierarchy B and Z
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) corresponds to version hierarchy C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) Each level of hierarchy is represented by a 32 bit value, and so there can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) only 32 different supported version per hierarchy. i.e. 1 bit per version. A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) value of 0xFFFFFFFF will enable the OPP for all versions for that hierarchy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) level. And a value of 0x00000000 will disable the OPP completely, and so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) never want that to happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) If 32 values aren't sufficient for a version hierarchy, than that version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) hierarchy can be contained in multiple 32 bit values. i.e. <X Y Z1 Z2> in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) above example, Z1 & Z2 refer to the version hierarchy Z.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - status: Marks the node enabled/disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) Example for a Juno with 1 clock and 1 regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) gpu_opp_table: opp_table0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) compatible = "operating-points-v2", "operating-points-v2-mali";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) opp@112500000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) opp-hz = /bits/ 64 <112500000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) opp-hz-real = /bits/ 64 <450000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) opp-microvolt = <820000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) opp-core-mask = /bits/ 64 <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) opp-suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) opp-mali-errata-1485982;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) opp@225000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) opp-hz = /bits/ 64 <225000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) opp-hz-real = /bits/ 64 <450000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) opp-microvolt = <820000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) opp-core-count = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) opp@450000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) opp-hz = /bits/ 64 <450000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) opp-hz-real = /bits/ 64 <450000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) opp-microvolt = <820000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) opp-core-mask = /bits/ 64 <0xf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) opp@487500000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) opp-hz = /bits/ 64 <487500000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) opp-microvolt = <825000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) opp@525000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) opp-hz = /bits/ 64 <525000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) opp-microvolt = <850000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) opp@562500000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) opp-hz = /bits/ 64 <562500000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) opp-microvolt = <875000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) opp@600000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) opp-hz = /bits/ 64 <600000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) opp-microvolt = <900000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) Example for a Juno with 2 clocks and 2 regulators:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) gpu_opp_table: opp_table0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) compatible = "operating-points-v2", "operating-points-v2-mali";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) opp@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) opp-hz = /bits/ 64 <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) opp-hz-real = /bits/ 64 <50000000>, /bits/ 64 <45000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) opp-microvolt = <820000>, <800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) opp-core-mask = /bits/ 64 <0xf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) opp@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) opp-hz = /bits/ 64 <40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) opp-hz-real = /bits/ 64 <40000000>, /bits/ 64 <35000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) opp-microvolt = <720000>, <700000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) opp-core-mask = /bits/ 64 <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) opp@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) opp-hz = /bits/ 64 <30000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) opp-hz-real = /bits/ 64 <30000000>, /bits/ 64 <25000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) opp-microvolt = <620000>, <700000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) opp-core-mask = /bits/ 64 <0x3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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