^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) OMAP CONTROL PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible: Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) e.g. USB2_PHY on OMAP5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) e.g. USB3 PHY and SATA PHY on OMAP5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) set PCS delay value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) e.g. PCIE PHY in DRA7x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) DRA7 platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) AM437 platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg : register ranges as listed in the reg-names property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - reg-names: "otghs_control" for control-phy-otghs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "power", "pcie_pcs" and "control_sma" for control-phy-pcie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "power" for all other types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) omap_control_usb: omap-control-usb@4a002300 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) compatible = "ti,control-phy-otghs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) reg = <0x4a00233c 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) reg-names = "otghs_control";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) TI PIPE3 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - reg : Address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - reg-names: The names of the register addresses corresponding to the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) filled in "reg".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - #phy-cells: determine the number of cells that should be given in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) phandle while referencing this phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - clocks: a list of phandles and clock-specifier pairs, one for each entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - clock-names: should include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * "wkupclk" - wakeup clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * "sysclk" - system clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * "refclk" - reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * "dpll_ref" - external dpll ref clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * "dpll_ref_m2" - external dpll ref clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * "phy-div" - divider for apll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * "div-clk" - apll clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - id: If there are multiple instance of the same type, in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) differentiate between each instance "id" can be used (e.g., multi-lane PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PHY). If "id" is not provided, it is set to default value of '1'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - syscon-pllreset: Handle to system control region that contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) register offset to write the PCS delay value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Deprecated properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - ctrl-module : phandle of the control module used by PHY driver to power on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) the PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Recommended properies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - syscon-phy-power : phandle/offset pair. Phandle to the system control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) module and the register offset to power on/off the PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) This is usually a subnode of ocp2scp to which it is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) usb3phy@4a084400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) compatible = "ti,phy-usb3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg = <0x4a084400 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) <0x4a084800 0x64>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) <0x4a084c00 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg-names = "phy_rx", "phy_tx", "pll_ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ctrl-module = <&omap_control_usb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clocks = <&usb_phy_cm_clk32k>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) <&sys_clkin>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) <&usb_otg_ss_refclk960m>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clock-names = "wkupclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "sysclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "refclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sata_phy: phy@4a096000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compatible = "ti,phy-pipe3-sata";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg = <0x4A096000 0x80>, /* phy_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) <0x4A096400 0x64>, /* phy_tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) <0x4A096800 0x40>; /* pll_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reg-names = "phy_rx", "phy_tx", "pll_ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ctrl-module = <&omap_control_sata>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clocks = <&sys_clkin1>, <&sata_ref_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clock-names = "sysclk", "refclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) syscon-pllreset = <&scm_conf 0x3fc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags