^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) -------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible : should be one of the listed compatibles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - "samsung,s5pv210-mipi-video-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - "samsung,exynos5420-mipi-video-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - "samsung,exynos5433-mipi-video-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - #phy-cells : from the generic phy bindings, must be 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) In case of s5pv210 and exynos5420 compatible PHYs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - syscon - phandle to the PMU system controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) In case of exynos5433 compatible PHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - samsung,pmu-syscon - phandle to the PMU system controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - samsung,disp-sysreg - phandle to the DISP system registers controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - samsung,cam0-sysreg - phandle to the CAM0 system registers controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - samsung,cam1-sysreg - phandle to the CAM1 system registers controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) the PHY specifier identifies the PHY and its meaning is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 0 - MIPI CSIS 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 1 - MIPI DSIM 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 2 - MIPI CSIS 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 3 - MIPI DSIM 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) supports additional fifth PHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 4 - MIPI CSIS 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Samsung Exynos SoC series Display Port PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) -------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - compatible : should be one of the following supported values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - "samsung,exynos5250-dp-video-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - "samsung,exynos5420-dp-video-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - samsung,pmu-syscon: phandle for PMU system controller interface, used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) control pmu registers for power isolation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - #phy-cells : from the generic PHY bindings, must be 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Samsung S5P/Exynos SoC series USB PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) -------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - compatible : should be one of the listed compatibles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - "samsung,exynos3250-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - "samsung,exynos4210-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - "samsung,exynos4x12-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - "samsung,exynos5250-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - "samsung,s5pv210-usb2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - reg : a list of registers used by phy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - first and obligatory is the location of phy modules registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - samsung,sysreg-phandle - handle to syscon used to control the system registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - samsung,pmureg-phandle - handle to syscon used to control PMU registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - #phy-cells : from the generic phy bindings, must be 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - clocks and clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - the "phy" clock is required by the phy module, used as a gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - the "ref" clock is used to get the rate of the clock provided to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PHY module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - vbus-supply: power-supply phandle for vbus power source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) The first phandle argument in the PHY specifier identifies the PHY, its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) and Exynos 4212) it is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0 - USB device ("device"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 1 - USB host ("host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 2 - HSIC0 ("hsic0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 3 - HSIC1 ("hsic1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Exynos3250 has only USB device phy available as phy 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) register is supplied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) For Exynos 4412 (compatible with Exynos 4212):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) usbphy: phy@125b0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) compatible = "samsung,exynos4x12-usb2-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reg = <0x125b0000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clocks = <&clock 305>, <&clock 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clock-names = "phy", "ref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) samsung,sysreg-phandle = <&sys_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) samsung,pmureg-phandle = <&pmu_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) Then the PHY can be used in other nodes such as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) phy-consumer@12340000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) phys = <&usbphy 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) phy-names = "phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Refer to DT bindings documentation of particular PHY consumer devices for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) information about required PHYs and the way of specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Samsung SATA PHY Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Each SATA PHY controller should have its own node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - compatible : compatible list, contains "samsung,exynos5250-sata-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) - reg : offset and length of the SATA PHY register set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) - #phy-cells : must be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) - clocks : must be exactly one entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) - clock-names : must be "sata_phyctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) - samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) - samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) sata_phy: sata-phy@12170000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) compatible = "samsung,exynos5250-sata-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg = <0x12170000 0x1ff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clocks = <&clock 287>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clock-names = "sata_phyctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) samsung,syscon-phandle = <&pmu_syscon>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) Device-Tree bindings for sataphy i2c client driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) --------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) compatible: Should be "samsung,exynos-sataphy-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) - reg: I2C address of the sataphy i2c device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) sata_phy_i2c:sata-phy@38 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) compatible = "samsung,exynos-sataphy-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg = <0x38>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) Samsung Exynos5 SoC series USB DRD PHY controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) --------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) - compatible : Should be set to one of the following supported values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) - reg : Register offset and length of USB DRD PHY register set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) - clocks: Clock IDs array as required by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) - clock-names: names of clocks correseponding to IDs in the clock property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) Required clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) used for register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) - ref: PHY's reference clock (usually crystal clock), used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PHY operations, associated by phy name. It is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) determine bit values for clock settings register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) - optional clocks: Exynos5433 & Exynos7 SoC has now following additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gate clocks available:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) - phy_pipe: for PIPE3 phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) - phy_utmi: for UTMI+ phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) - itp: for ITP generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) - samsung,pmu-syscon: phandle for PMU system controller interface, used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) control pmu registers for power isolation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) - #phy-cells : from the generic PHY bindings, must be 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) compatible PHYs, the second cell in the PHY specifier identifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PHY id, which is interpreted as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0 - UTMI+ type phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 1 - PIPE3 type phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) usbdrd_phy: usbphy@12100000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) compatible = "samsung,exynos5250-usbdrd-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) reg = <0x12100000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clocks = <&clock 286>, <&clock 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clock-names = "phy", "ref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) samsung,pmu-syscon = <&pmu_system_controller>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 'usbdrd_phy' nodes should have numbered alias in the aliases node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) in the form of usbdrdphyN, N = 0, 1... (depending on number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) controllers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) aliases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) usbdrdphy0 = &usb3_phy0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) usbdrdphy1 = &usb3_phy1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) Samsung Exynos SoC series PCIe PHY controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) --------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) - compatible : Should be set to "samsung,exynos5440-pcie-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) - #phy-cells : Must be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) - reg : a register used by phy driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) - First is for phy register, second is for block register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) - reg-names : Must be set to "phy" and "block".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pcie_phy0: pcie-phy@270000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) compatible = "samsung,exynos5440-pcie-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) reg = <0x270000 0x1000>, <0x271000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg-names = "phy", "block";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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