Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ROCKCHIP USB2 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible: matching the soc type, one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)      "rockchip,rk3066a-usb-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)      "rockchip,rk3188-usb-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)      "rockchip,rk3288-usb-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - #address-cells: should be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - #size-cells: should be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Deprecated properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - rockchip,grf : phandle to the syscon managing the "general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)    register files" - phy should be a child of the GRF instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Sub-nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Each PHY should be represented as a sub-node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Sub-nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - #phy-cells: should be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg: PHY configure reg address offset in GRF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		"0x320" - for PHY attach to OTG controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		"0x334" - for PHY attach to HOST0 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		"0x348" - for PHY attach to HOST1 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Optional Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - clocks : phandle + clock specifier for the phy clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - clock-names: string, clock name, must be "phyclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - #clock-cells: for users of the phy-pll, should be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - reset-names: Only allow the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  - phy-reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - resets: Must contain an entry for each entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - vbus-supply: power-supply phandle for vbus power source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) grf: syscon@ff770000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	usbphy: phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		compatible = "rockchip,rk3288-usb-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		usbphy0: usb-phy0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			reg = <0x320>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };