Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Rockchip PCIE PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  - compatible: rockchip,rk3399-pcie-phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  - clocks: Must contain an entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - clock-names: Must be "refclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - resets: Must contain an entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - reset-names: Must be "phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Required properties for legacy PHY mode (deprecated):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - #phy-cells: must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Required properties for per-lane PHY mode (preferred):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  - #phy-cells: must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) grf: syscon@ff770000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	pcie_phy: pcie-phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		compatible = "rockchip,rk3399-pcie-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		clocks = <&cru SCLK_PCIEPHY_REF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		clock-names = "refclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		resets = <&cru SRST_PCIEPHY>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		reset-names = "phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };