Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Helen Koike <helen.koike@collabora.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - Ezequiel Garcia <ezequiel@collabora.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     const: rockchip,rk3399-mipi-dphy-rx0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)       - description: MIPI D-PHY ref clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)       - description: MIPI D-PHY RX0 cfg clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)       - description: Video in/out general register file clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)       - const: dphy-ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)       - const: dphy-cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)       - const: grf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   '#phy-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     const: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)     description: Video in/out power domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   - '#phy-cells'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   - power-domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)     /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)      * MIPI D-PHY RX0 use registers in "general register files", it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)      * should be a child of the GRF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)      *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)      * grf: syscon@ff770000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)      *  compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)      *  ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)      * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)     #include <dt-bindings/clock/rk3399-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)     #include <dt-bindings/power/rk3399-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)     mipi_dphy_rx0: mipi-dphy-rx0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)         compatible = "rockchip,rk3399-mipi-dphy-rx0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)         clocks = <&cru SCLK_MIPIDPHY_REF>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)                  <&cru SCLK_DPHY_RX0_CFG>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)                  <&cru PCLK_VIO_GRF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)         clock-names = "dphy-ref", "dphy-cfg", "grf";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)         power-domains = <&power RK3399_PD_VIO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)         #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)     };