Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Rockchip EMMC PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  - compatible: rockchip,rk3399-emmc-phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  - #phy-cells: must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - reg: PHY register address offset and length in "general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)    register files"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - clock-names: Should contain "emmcclk".  Although this is listed as optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		(because most boards can get basic functionality without having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		access to it), it is strongly suggested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		See ../clock/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - drive-impedance-ohm: Specifies the drive impedance in Ohm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)                         Possible values are 33, 40, 50, 66 and 100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)                         If not set, the default value of 50 will be applied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) grf: syscon@ff770000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	emmcphy: phy@f780 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		compatible = "rockchip,rk3399-emmc-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		reg = <0xf780 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		clocks = <&sdhci>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		clock-names = "emmcclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		drive-impedance-ohm = <50>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };