Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Qualcomm PCIe2 PHY controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) =============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - compatible: compatible list, should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - reg: offset and length of the PHY register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - #phy-cells: must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - clocks: a clock-specifier pair for the "pipe" clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - vdda-vp-supply: phandle to low voltage regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  - vdda-vph-supply: phandle to high voltage regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  - resets: reset-specifier pairs for the "phy" and "pipe" resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  - reset-names: list of resets, should contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		"phy" and "pipe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  - clock-output-names: name of the outgoing clock signal from the PHY PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  - #clock-cells: must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  phy@7786000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	reg = <0x07786000 0xb8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	         <&gcc GCC_PCIE_0_PIPE_ARES>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	reset-names = "phy", "pipe";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	vdda-vp-supply = <&vreg_l3_1p05>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	vdda-vph-supply = <&vreg_l5_1p8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	clock-output-names = "pcie_0_pipe_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  };