Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Qualcomm APQ8064 SATA PHY Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Each SATA PHY controller should have its own node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: compatible list, contains "qcom,apq8064-sata-phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: offset and length of the SATA PHY register set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #phy-cells: must be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks: a list of phandles and clock-specifier pairs, one for each entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clock-names: must be "cfg" for phy config clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	sata_phy: sata-phy@1b400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		compatible = "qcom,apq8064-sata-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		reg = <0x1b400000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		clocks = <&gcc SATA_PHY_CFG_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		clock-names = "cfg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	};