^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Marvell PXA1928 USB and HSIC PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: base address and length of the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - clocks - A single clock. From common clock binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - #phys-cells: should be 0. From commmon phy binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - resets: reference to the reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) usbphy: phy@7000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) compatible = "marvell,pxa1928-usb-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) reg = <0x7000 0xe0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) clocks = <&apmu_clocks PXA1928_CLK_USB>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)