Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) STMicroelectronics STM32 USB HS PHY controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) switch. It controls PHY configuration and status, and the UTMI+ switch that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) selects either OTG or HOST controller for the second PHY port. It also sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) PLL configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) USBPHYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)       |_ PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)       |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)       |_ PHY port#1 _________________ HOST controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)       |                    _                 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)       |                  / 1|________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)       |_ PHY port#2 ----|   |________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)       |                  \_0|                |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)       |_ UTMI switch_______|          OTG controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Phy provider node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - compatible: must be "st,stm32mp1-usbphyc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - reg: address and length of the usb phy control register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clocks: phandle + clock specifier for the PLL phy clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - #address-cells: number of address cells for phys sub-nodes, must be <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - #size-cells: number of size cells for phys sub-nodes, must be <0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - assigned-clocks: phandle + clock specifier for the PLL phy clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - assigned-clock-parents: the PLL phy clock parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - resets: phandle + reset specifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Required nodes: one sub-node per port the controller provides.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Phy sub-nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - reg: phy port index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - phy-supply: phandle to the regulator providing 3V3 power to the PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	      see phy-bindings.txt in the same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   port#1 and must be <1> for PHY port#2, to select USB controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		usbphyc: usb-phy@5a006000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			compatible = "st,stm32mp1-usbphyc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			reg = <0x5a006000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			clocks = <&rcc_clk USBPHY_K>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			resets = <&rcc_rst USBPHY_R>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			usbphyc_port0: usb-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 				reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 				phy-supply = <&vdd_usb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 				vdda1v1-supply = <&reg11>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 				vdda1v8-supply = <&reg18>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 				#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			usbphyc_port1: usb-phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 				reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 				phy-supply = <&vdd_usb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 				vdda1v1-supply = <&reg11>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 				vdda1v8-supply = <&reg18>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 				#phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		};