^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ROCKCHIP USB2.0 PHY WITH NANENG IP BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties (phy (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : should be one of the listed compatibles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * "rockchip,rv1126-usb2phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg : the address offset of grf for usb-phy configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - rockchip,grf : phandle to the syscon managing the "general register files"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - clocks : phandle + phy specifier pair, for the input clocks of phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - clock-names : input clocks name of phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - resets : phandle + reset specifier pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reset-names : reset names of phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #clock-cells : should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clock-output-names : specify the 480m output clock name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - assigned-clocks : phandle of usb 480m clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - assigned-clock-parents : parent of usb 480m clock, select between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) usb-phy output 480m and xin24m.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Refer to clk/clock-bindings.txt for generic clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) consumer properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - vbus-supply : regulator phandle for vbus power source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - wakeup-source : enable bvalid irq and linestate wakeup when suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) only work when suspend wakeup-config is not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - vup-gpios : gpio phandle for pull-up resistor on DM. this property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) is specially provided to RV1126/RV1109 in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) increase the amplitude of chirpK and successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) complete high speed handshake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Required nodes : a sub-node is required for each port the phy provides.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) The sub-node name is used to identify host or otg port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) and shall be the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * "otg-port" : the name of otg port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * "host-port" : the name of host port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Required properties (port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - #phy-cells : must be 0. See ./phy-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - interrupts : specify an interrupt for each entry in interrupt-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - interrupt-names : a list which should be one of the following cases:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Regular case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * "otg-id" : for the otg id interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * "otg-bvalid" : for the otg vbus interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * "linestate" : for the host/otg linestate interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * "disconnect" : for the host/otg disconnect interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - phy-supply : phandle to a regulator that provides power to VBUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) See ./phy-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - rockchip,vbus-always-on: when set, indicates that the otg vbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) is always powered on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u2phy1: usb2-phy@ff4c8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) compatible = "rockchip,rv1126-usb2phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg = <0xff4c8000 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) rockchip,grf = <&grf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clock-names = "phyclk", "pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) assigned-clocks = <&cru USB480M>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) assigned-clock-parents = <&u2phy1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reset-names = "u2phy", "u2phy-apb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clock-output-names = "usb480m_phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u2phy_host: host-port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) interrupt-names = "linestate", "disconnect";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };