Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Rockchip Naneng eDP Transmitter PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible:	should be "rockchip,rk3568-edp-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg:		register range for the PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - clocks:	Must contain an entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 		See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names:	Must contain "refclk" and "pclk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - resets:	Must contain an entry for each in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reset-names:	Must contain "apb".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #phy-cells:	Must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	edp_phy: edp-phy@fdcb0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		compatible = "rockchip,rk3568-edp-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		reg = <0x0 0xfdcb0000 0x0 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		clock-names = "refclk", "pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		resets = <&cru SRST_P_EDPPHY_GRF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		reset-names = "apb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	};