Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ROCKCHIP COMBO PHY WITH NANENG IP BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties (phy (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible : should be one of the listed compatibles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	* "rockchip,rk3568-naneng-combphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  - reg : the address offset of grf for combo-phy configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - rockchip,pipe-grf : phandle to the syscon managing the "pipe general register files"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - rockchip,pipe-phy-grf: phandle to the syscon managing the "phy general register files"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - clocks : phandle + phy specifier pair, for the input clocks of phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - clock-names : input clocks name of phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - resets : phandle + reset specifier pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - reset-names : reset names of phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  - #clock-cells : should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - assigned-clocks : phandle of refclk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  - assigned-clock-parents : parent of clk_xxx_osc or clk_xxx_div.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		 Refer to clk/clock-bindings.txt for generic clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		 consumer properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  - rockchip,dis-u3otg0-port: when set, disable the u3 root port of otg0 host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  - rockchip,dis-u3otg1-port: when set, disable the u3 root port of otg1 host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) combphy0: phy@fe820000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	compatible = "rockchip,rk3568-naneng-combphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	reg = <0x0 0xfe820000 0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	#phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	clock-names = "refclk", "apbclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	reset-names = "combphy-apb", "combphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	rockchip,pipe-grf = <&pipegrf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };