Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ROCKCHIP MIPI/LVDS/TTL VIDEO COMBO PHY WITH INNO IP BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible : must be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	"rockchip,px30-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	"rockchip,rk3128-video-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	"rockchip,rk3368-video-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	"rockchip,rk3568-video-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - reg : the address offset of register for phy and host configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - #phy-cells : must be 0. See ./phy-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - clocks: must include clock specifiers corresponding to entries in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	   clock-names property. See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  - clock-names: list of clock names sorted in the same order as the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		property. Must contain "ref", "pclk_phy", "pclk_host".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - #clock-cells : from common clock binding; shall be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - resets : phandle to the reset of phy apb clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  - reset-names : should be "rst".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  - power-domains: Must contain a reference to the PM domain, if available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	video_phy: video-phy@ff2e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		compatible = "rockchip,px30-video-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		reg = <0x0 0xff2e0000 0x0 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		      <0x0 0xff450000 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		clocks = <&pmucru SCLK_MIPIDSIPHY_REF>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			 <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		clock-names = "ref", "pclk_phy", "pclk_host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		resets = <&cru SRST_MIPIDSIPHY_P>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		reset-names = "rst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		power-domains = <&power PX30_PD_VO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	};