^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties (phy (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: should be one of the listed compatibles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * "rockchip,rk3328-u3phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * "rockchip,rk322xh-u3phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - reg : the base address of USB 3.0 PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - rockchip,u3phygrf : phandle to the syscon managing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "USB 3.0 PHY general register files".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts : specify an interrupt for each entry in interrupt-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupt-names : a list which shall be the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * "linestate" : for the host/otg linestate interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks : phandle + clock specifier for the phy clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * "u3phy-otg" for USB 3.0 PHY utmi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * "u3phy-pipe" for USB 3.0 PHY pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - resets : a list of phandle + reset specifier pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - reset-names :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * "u3phy-u2-por" for the USB 2.0 logic of USB 3.0 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * "u3phy-u3-por" for the USB 3.0 logic of USB 3.0 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * "u3phy-pipe-mac" for the USB 3.0 PHY pipe MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * "u3phy-utmi-mac" for the USB 3.0 PHY utmi MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * "u3phy-utmi-apb" for the USB 3.0 PHY utmi apb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * "u3phy-pipe-apb" for the USB 3.0 PHY pipe apb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - vbus-supply: regulator phandle for vbus power source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Required nodes : a sub-node is required for USB 3.0 or USB 2.0 the phy provides.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) The sub-node name is used to identify phy type, and shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * "u3phy_utmi" : USB 2.0 utmi phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * "u3phy_pipe" : USB 3.0 pipe phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Required properties (port (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - reg : address and length of the register set for the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - #phy-cells : must be 0. See ./phy-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Optional properties for utmi node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - rockchip,odt-val-tuning : specify 45ohm ODT tuning value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Optional properties for pipe node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - rockchip,refclk-25m-quirk : phy reference clock changed to 25m quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) usb3phy_grf: syscon@ff460000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) compatible = "rockchip,usb3phy-grf", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = <0x0 0xff460000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u3phy: usb3-phy@ff470000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) compatible = "rockchip,rk3328-u3phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) reg = <0x0 0xff470000 0x0 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) rockchip,u3phygrf = <&usb3phy_grf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) interrupt-names = "linestate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) clock-names = "u3phy-otg", "u3phy-pipe";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) resets = <&cru SRST_USB3PHY_U2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) <&cru SRST_USB3PHY_U3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) <&cru SRST_USB3PHY_PIPE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) <&cru SRST_USB3OTG_UTMI>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) <&cru SRST_USB3PHY_OTG_P>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) <&cru SRST_USB3PHY_PIPE_P>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reset-names = "u3phy-u2-por", "u3phy-u3-por",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "u3phy-pipe-mac", "u3phy-utmi-mac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "u3phy-utmi-apb", "u3phy-pipe-apb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u3phy_utmi: utmi@ff470000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg = <0x0 0xff470000 0x0 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u3phy_pipe: pipe@ff478000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg = <0x0 0xff478000 0x0 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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