Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ROCKCHIP MIPI DPHY WITH INNO IP BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible : must be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	"rockchip,rk1808-mipi-dphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	"rockchip,rv1126-mipi-dphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - reg : the address offset of register for mipi-dphy configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - #phy-cells : must be 0. See ./phy-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - clocks and clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	- the "pclk" clock is required by the phy module, used to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	  configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	- the "ref" clock is used to get the rate of the reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	  provided to the PHY module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - clock-output-names: from common clock binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - #clock-cells : from common clock binding; shall be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  - resets : phandle to the reset of MIPI DSI PHY APB clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  - reset-names : should be "apb".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	mipi_dphy: mipi-dphy@ff370000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		compatible = "rockchip,rk1808-mipi-dphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		reg = <0x0 0xff370000 0x0 0x500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		clock-names = "ref", "pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		clock-output-names = "mipi_dphy_pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		resets = <&cru SRST_MIPIDSIPHY_P>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		reset-names = "apb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		rockchip,grf = <&grf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	};