Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ROCKCHIP HDMI PHY WITH INNO IP BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible : should be one of the listed compatibles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	* "rockchip,rk3228-hdmi-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	* "rockchip,rk3328-hdmi-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - reg : Address and length of the hdmi phy control register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - clocks : phandle + clock specifier for the phy clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - clock-names : string, clock name, must contain "sysclk" for system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	  control and register configuration, "refoclk" for crystal-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	  oscillator reference PLL clock input and "refpclk" for pclk-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	  based refeference PLL clock input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  - #clock-cells: should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - clock-output-names : shall be the name for the output clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - interrupts : phandle + interrupt specified for the hdmiphy interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - #phy-cells : must be 0. See ./phy-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Optional properties for rk3328-hdmi-phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  - nvmem-cells = phandle + nvmem specifier for the cpu-version efuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  - nvmem-cell-names : "cpu-version" to read the chip version, required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	  for adjustment to some frequency settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	hdmi_phy: hdmi-phy@12030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "rockchip,rk3228-hdmi-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		reg = <0x12030000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		clock-names = "sysclk", "refoclk", "refpclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		clock-output-names = "hdmi_phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Then the PHY can be used in other nodes such as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	hdmi: hdmi@200a0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		compatible = "rockchip,rk3228-dw-hdmi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		phys = <&hdmi_phy>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		phy-names = "hdmi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	};